35#ifndef ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
36#define ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
41#define MEM_ACC_CACHE_DEFAULT_PAGE_SIZE 2048
42#define MEM_ACC_CACHE_DEFAULT_MRU_SIZE 16
43#define MEM_ACC_CACHE_PAGE_SIZE_MAX 16384
44#define MEM_ACC_CACHE_MRU_SIZE_MAX 256
45#define MEM_ACC_CACHE_PAGE_SIZE_MIN 64
46#define MEM_ACC_CACHE_MRU_SIZE_MIN 4
48#define OCSD_ENV_MEMACC_CACHE_OFF "OPENCSD_MEMACC_CACHE_OFF"
49#define OCSD_ENV_MEMACC_CACHE_PG_SIZE "OPENCSD_MEMACC_CACHE_PAGE_SIZE"
50#define OCSD_ENV_MEMACC_CACHE_PG_NUM "OPENCSD_MEMACC_CACHE_PAGE_NUM"
89 const bool enabled()
const {
return m_bCacheEnabled; };
92 return (m_bCacheEnabled && (reqSize <= m_mru_page_size));
110 bool blockInCache(
const ocsd_vaddr_t address,
const uint32_t reqBytes,
const uint8_t trcID);
111 bool blockInPage(
const ocsd_vaddr_t address,
const uint32_t reqBytes,
const uint8_t trcID);
118 void destroyCaches();
122 uint16_t m_mru_page_size;
124 uint32_t m_mru_sequence;
126 bool m_bCacheEnabled =
false;
128#ifdef LOG_CACHE_STATS
130 uint32_t m_misses = 0;
131 uint32_t m_pages = 0;
132 uint32_t* m_hit_rl = 0;
133 uint32_t* m_hit_rl_max = 0;
140 m_mru(0), m_mru_sequence(1)
153inline bool TrcMemAccCache::blockInPage(
const ocsd_vaddr_t address,
const uint32_t reqBytes,
const uint8_t trcID)
156 if ((m_mru[m_mru_idx].trcID != trcID) ||
157 (m_mru[m_mru_idx].valid_len == 0)
162 if ((m_mru[m_mru_idx].st_addr <= address) &&
163 m_mru[m_mru_idx].st_addr + m_mru[m_mru_idx].valid_len >= (address + reqBytes))
168inline bool TrcMemAccCache::blockInCache(
const ocsd_vaddr_t address,
const uint32_t reqBytes,
const uint8_t trcID)
170 int tests = m_mru_num_pages;
173 if (blockInPage(address, reqBytes, trcID))
175#ifdef LOG_CACHE_STATS
177 if (tests == m_mru_num_pages)
183 if (m_mru_idx == m_mru_num_pages)
static void getenvMemaccCacheSizes(bool &enable, int &page_size, int &num_pages)
void invalidateByTraceID(int8_t trcID)
ocsd_err_t setCacheSizes(const uint16_t page_size, const int nr_pages, const bool err_on_limit=false)
const bool enabled_for_size(const uint32_t reqSize) const
ocsd_err_t readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer)
const bool enabled() const
ocsd_err_t enableCaching(bool bEnable)
void clearPage(cache_block_t *page)
void setErrorLog(ITraceErrorLog *log)
Memory range to access by trace decoder.
#define OCSD_BAD_CS_SRC_ID
enum _ocsd_mem_space_acc_t ocsd_mem_space_acc_t
enum _ocsd_err_t ocsd_err_t
OpenCSD : Standard Types used in the library interfaces.
struct cache_block cache_block_t
#define MEM_ACC_CACHE_DEFAULT_MRU_SIZE
#define MEM_ACC_CACHE_DEFAULT_PAGE_SIZE